1. Field of the Invention
The present invention relates to amplifier circuits in general and, more particularly, to amplifier circuits for implementation on an integrated circuit chip with a digital fabricating process.
2. Prior Art
Semiconductor technology has progressed to the point where entire systems (such as logic circuits, memory circuits, microprocessor circuits, analog circuits, etc.) are being integrated on a single silicon chip. Due to the wide range of functions, trade-offs between individual function optimization and overall process capability must be made. Since the logic and memory functions represent the majority of the total system circuitry, the fabricating process is usually designed to optimize these functions. Among the available processes, the CMOS process appears to be the most effective and widely used to fabricate Very Large Scale Integration (VLSI) chips.
One of the cost reduction characteristics of the CMOS technology is that it operates on a single power supply level (usually +5 V). This is made possible because digital circuits are either "ON" or "OFF." In contrast, analog circuits, such as amplifiers, must be operated in their linear region where circuit nodes must be biased at a voltage level somewhere between the power supply level and ground. Providing an intermediate biasing voltage has always been a problem in CMOS technology, since extraneous process steps and/or devices are needed. This, in turn, tends to increase the product cost and negate some of the favorable characteristics that make the CMOS process attractive for fabricating mixed circuit VLSI chips.
Mixed circuit VLSI chips with precision gain amplifiers have been designed in CMOS technology using switched capacitor techniques. An example of this technique is set forth in an article entitled "Switched-Capacitor Circuit Design" by Gregorian, R. et al, Procedures of IEEE. Even though the technique works well for its intended purpose, its main drawback is that it requires clocks and sampling techniques to extract the amplified signal. As a result, the switched capacitor approach cannot handle signals whose frequency approaches the frequency limit of the technology. In addition, the switched capacitor technique is a sampled one and does not provide continuous amplification. Also, switched capacitor circuits consume large amounts of chip area and introduce noise into the signal.
An amplifier structure that provides continuous amplification has been designed in NMOS technology. An example of the amplifier structure is given in U.S. Pat. No. 4,659,811. In that patent a pair of depletion mode devices (biased in their linear regions with their combined current equal to a constant value) in the feedback of an operational amplifier control the gain of the amplifier. The major drawback with this design is that depletion mode FETs are not available in CMOS technology. Also, a multi-rail power supply is needed. As argued above, multi-rail power supplies are not economically attractive and efforts are made to avoid their use in CMOS technology.